1. Field of the Invention
The present invention relates generally to memory, and more specifically to address and data protocol for a memory device.
2. Description of the Related Art
The demand for more powerful computers and circuit boards has led to advances in the technology industry. However, a designer struggles with improving performance while minimizing the amount of pins needed for the design. For example, if a printed circuit board (PCB) is designed for a cellular application, the PCB designer needs to incorporate performance features such as supporting wireless standards and audio/video transmission and reception. However, the PCB designer also needs to minimize the size of the PCB by minimizing the number of pins to improve manufacturing efficiency because of the difficulty of routing signals on a large PCB with a substantial number of functional pins.
A typical solution, Address-Data Multiplexed Protocol, is illustrated in FIG. 1. The timing diagram 100 illustrates a protocol for multiplexing address and data information on pins, and IN and OUT refers to whether the information is being received by the memory device (IN) or is being sent by the memory device (OUT). The address pins are designated as 110, and are labeled A[7:0] to indicate eight address bits. The data pins are designated as 120, and are labeled D[15:0] to indicate sixteen data bits. This protocol allows the data pins to serve multiple functions based on a control pin and the direction of communication between the central processor unit (CPU) and the memory. For example, the CPU needs to send a read request to the memory with twenty-four bits of address information. However, the eight address pins are not sufficient to transmit the read request in one clock cycle. To solve this problem, the sixteen data pins are used to send the rest of the address information to the memory device. After the memory has retrieved the data based on the address of the read request sent during clock cycle t0, the memory sends the information on the data pins back to the CPU during clock cycle t7.
Another typical solution, Addressxe2x80x94Address Multiplexed Protocol, is illustrated in FIG. 2. The timing diagram 200 illustrates a protocol for multiplexing address information on pins. The row address strobe (RAS) 210, and column address strobe (CAS) 220 are the control signals. Both signals are labeled with a # to indicate the signals are active for a logic value of zero. The address pins are designated as 230 and are labeled A[11:0] to indicate twelve address bits. The data pins are designated as 240, and are labeled D[15:0] to indicate sixteen bits of data information. As an example, the CPU sends twelve address bits during clock cycle t0 when RAS# is low, and sends another twelve address bits during clock cycle t1 when CAS# is low. This protocol allows for the address pins to send twenty-four bits, while only utilizing twelve address pins. FIG. 3 illustrates the Addressxe2x80x94Address Multiplexed Protocol with a burst operation, wherein the memory device retrieves information based on the twenty four address bits for a read request sent during clock cycles t0 and t1. The memory sends the data associated with the read request during clock cycle t7. Also, the burst allows the memory device to send the data associated with the seven consecutive address locations during clock cycles t8-t14. The typical address protocols have a disadvantage.
Therefore, the Addressxe2x80x94Address Multiplexed Protocol degrades performance because it requires two clock cycles to send the address to the memory. In contrast, Address-Data Multiplexed Protocol sends the address in one clock cycle. However, this protocol does not support a burst as discussed in FIG. 3 since the data pins are occupied with data on clock cycle t7, and cannot send address information during clock cycle t7.
Another typical solution is designing a bus to transmit address, data, and control information in a time-multiplexed manner. However, this requires a complex state machine which increases design time and complexity.